Wybrane standardy I/O Intel Stratix 10
Źródło: Intel, Intel Stratix 10 Device Datasheet, 2023, strony PDF: 24, 29. Podpis w źródle: Table 21. Single-Ended I/O Standards Specifications; Table 27. Differential I/O Standards Specifications
Podstawowe poziomy napięć dla wybranych standardów I/O pojedynczych i różnicowych w FPGA Stratix 10.
Pokazano 10 z 10 wierszy.
| Standard | Tryb | VCCIO typ [V] | VIL max | VIH min | VID min [mV] | VOD typ [V] |
|---|---|---|---|---|---|---|
| 3.3 V LVTTL / 3.3 V LVCMOS | single-ended | 3.3 | 0.8 V | 2.0 V | ||
| 3.0 V LVTTL / 3.0 V LVCMOS | single-ended | 3 | 0.8 V | 2.0 V | ||
| 2.5 V | single-ended | 2.5 | 0.7 V | 1.7 V | ||
| 1.8 V | single-ended | 1.8 | 0.35 x VCCIO | 0.65 x VCCIO | ||
| 1.5 V | single-ended | 1.5 | 0.35 x VCCIO | 0.65 x VCCIO | ||
| 1.2 V | single-ended | 1.2 | 0.35 x VCCIO | 0.65 x VCCIO | ||
| LVDS | differential | 1.8 | 100 | |||
| RSDS | differential | 1.8 | 100 | 0.2 | ||
| Mini-LVDS | differential | 1.8 | 200 | |||
| LVPECL | differential | 1.8 | 300 |