Cechy transceiverów GTY UltraScale
Źródło: Xilinx, UltraScale Architecture GTY Transceivers User Guide UG578, v1.1, 2015, strony PDF: 10-11. Podpis w źródle: Table 1-1: GTY Transceiver Features
Lista funkcji warstw PCS i PMA transceiverów GTY: kodowanie, korekcja zegara, FIFO, PLL, equalizacja i obsługiwane prędkości.
Pokazano 22 z 22 wierszy.
| Grupa | Cecha |
|---|---|
| PCS | 2-byte, 4-byte, and 8-byte internal datapath to support different line rate requirements |
| PCS | 8B/10B encoding and decoding |
| PCS | 64B/66B and 64B/67B support |
| PCS | 128B/130B encoding and decoding for PCI Express Gen3 |
| PCS | Comma detection and byte and word alignment |
| PCS | PRBS generator and checker |
| PCS | TX phase FIFO |
| PCS | RX elastic FIFO for clock correction and channel bonding |
| PCS | Buffer bypass support for fixed latency |
| PCS | Programmable logic interface |
| PCS | 100 Gb attachment unit interface (CAUI) support |
| PCS | Native multi-lane support for buffer bypass |
| PCS | TX phase interpolator PPM controller for external VCXO replacement |
| PMA | Two shared LC tank PLLs per Quad |
| PMA | One ring PLL per channel |
| PMA | Low-power mode adaptive linear equalizer |
| PMA | 15-tap decision feedback equalizer with auto adapt |
| PMA | TX pre-emphasis |
| PMA | Programmable TX output |
| PMA | Beacon signaling for PCI Express designs |
| PMA | Out-of-band signaling including COM signal support for SATA designs |
| PMA | Line rate up to 30.5 Gb/s for UltraScale FPGAs and 32.75 Gb/s for UltraScale+ FPGAs |