Zasoby pomocniczych bloków Transceivers Wizard
Źródło: Xilinx, UltraScale FPGAs Transceivers Wizard v1.7 Product Guide PG182, 2020, strony PDF: 11-12. Podpis w źródle: Table 2-1: Free-Running Clock Maximum Frequency; Table 2-2: Resource Utilization of Helper Blocks
Zasoby LUT/FF/buforów zegara dla opcjonalnych bloków pomocniczych generowanych przez Xilinx Transceivers Wizard.
Pokazano 10 z 10 wierszy.
| Blok pomocniczy | Konfiguracja | LUT | Przerzutniki | Bufory zegara |
|---|---|---|---|---|
| Reset controller | Any | 120 | 195 | 0 |
| Transmitter user clocking network | F_TXUSRCLK = F_TXUSRCLK2 | 0 | 2 | 1 BUFG_GT |
| Transmitter user clocking network | F_TXUSRCLK != F_TXUSRCLK2 | 0 | 2 | 2 BUFG_GT |
| Receiver user clocking network | F_RXUSRCLK = F_RXUSRCLK2 | 0 | 2 | 1 BUFG_GT |
| Receiver user clocking network | F_RXUSRCLK != F_RXUSRCLK2 | 0 | 2 | 2 BUFG_GT |
| Transmitter buffer bypass controller | Single-lane | 8 | 25 | 0 |
| Transmitter buffer bypass controller | Multi-lane | <20 | 25 | 0 |
| Receiver buffer bypass controller | Single-lane | 8 | 25 | 0 |
| Receiver buffer bypass controller | Multi-lane | <20 | 25 | 0 |
| User data width sizing | Any | 0 | 0 | 0 |